Photosensitive elements (e.g., photodiodes or photomultipliers) can output a current corresponding in amplitude to the intensity of incident light, thereby detecting the light intensity based on the current value. Such a photosensitive element has a good linearity between the intensity of incident light and the output current value over a wide dynamic range of the intensity of incident light. On the other hand, it is known that the dynamic range of the sensitivity of the human eye to the intensity of light is about six orders of magnitude.
In this context, an A/D converter for inputting the value of a current outputted from the photosensitive element for analog to digital conversion is required to output a digital value of a number of bits corresponding to the intensity of light over such a wide dynamic range. For example, corresponding to the dynamic range of light intensity being six orders of magnitude, the A/D converter is required to output a digital value of 20 bits. However, it is difficult to realize such an A/D converter that outputs a digital value of 20 bits.
To address such a problem, there has been suggested an I/F converter which outputs a signal at a frequency corresponding to the amplitude of inputted current (e.g., see Japanese Patent Application Laid-Open No. 2002-107428). This I/F converter inputs the value of a current outputted from the photosensitive element to output a pulsed signal at a frequency corresponding to the magnitude of the value of the current (i.e., the intensity of light made incident upon the photosensitive element). Accordingly, by counting the number of pulses per unit time in the signal outputted from the I/F converter, it is possible to obtain the light intensity as a digital value over a wide dynamic range.
FIG. 12 is a view illustrating the configuration of a conventional I/F converter disclosed in Japanese Patent Application Laid-Open No. 2002-107428. An I/F converter 40 illustrated in this figure includes a current-to-voltage converting circuit 41, a transistor Tr1, a current mirror circuits 42 and 43, a mirror integrator circuit 44, a comparator circuit 45, and a reference voltage source 46.
The current-to-voltage converting circuit 41, which has an operational amplifier 41a and a feedback resistive element Rf, inputs the current value outputted from a current value detecting circuit 4 and then converts it into a voltage value corresponding to the current value to output the voltage value. The transistor Tr1 inputs, at its gate terminal, the voltage value outputted from the current-to-voltage converting circuit 41, allowing the current of the value obtained by logarithmically amplifying the voltage value to flow between the source terminal and the drain terminal. The current mirror circuit 42, which has transistors Tr2 and Tr3, amplifies the current outputted from the transistor Tr1 for output. The current mirror circuit 43, which has transistors Tr4 and Tr5, amplifies the current outputted from the current mirror circuit 42 for output.
The mirror integrator circuit 44, which has an operational amplifier 44a and a feedback capacitive element C, inputs a current outputted from the current mirror circuit 43 to accumulate charges in the capacitive element C corresponding to the input current, and then outputs a voltage value corresponding to the amount of charges accumulated. The comparator circuit 45 compares amplitudes between the voltage value outputted from the mirror integrator circuit 44 and the reference voltage value Vref outputted from the reference voltage source 46 to output a comparison signal indicating the result of the comparison. A switch 34 disposed between the input and output terminals of the operational amplifier 44a of the mirror integrator circuit 44 inputs the comparison signal that has been outputted from the comparator circuit 45 and passed through a buffer amplifier 33, thereby being opened or closed in accordance with the comparison signal.
In the I/F converter 40, a current inputted to the mirror integrator circuit 44 gradually increases the amount of charges accumulated in the capacitive element C, thereby causing the value of the voltage outputted from the mirror integrator circuit 44 to increase. Then after the value of the voltage outputted from the mirror integrator circuit 44 exceeds the reference voltage value Vref, the comparison signal outputted from the comparator circuit 45 is inverted, thereby causing the switch 34 to be closed and the capacitive element C to be discharged. When the capacitive element C is discharged, the comparison signal is inverted again and the switch 34 is opened, thus starting building up charges in the capacitive element C. In this manner, charge and discharge operations repeatedly performed on the capacitive element C will cause the comparison signal outputted from the comparator circuit 45 to be turned into a signal that is representative of the repetition of the charge and discharge operations and at a frequency corresponding to the magnitude of the value of the input current.
The I/F converter 40 includes the transistor Tr1 that has a logarithmic amplification characteristic. This is intended to improve the input and output related linearity between the input current value and the output frequency even when use of a transistor having no logarithmic amplification characteristic would cause such a high output frequency (a large input current value) that cannot ensure a sufficient period of time for discharging the capacitive element C. In other words, the I/F converter 40 is intended to improve the input and output related linearity of the input current value over a wide dynamic range.